Datasheet
In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit is sent as shown in
Slave Behavioral Diagram (SCLSM=1). This strategy can be used when it is not necessary to check
DATA before acknowledging. For master reads, an address and data interrupt will be issued
simultaneously after the address acknowledge. However, for master writes, the first data interrupt will be
seen after the first data byte has been received by the slave and the acknowledge bit has been sent to
the master.
Note: For I
2
C High-speed mode (Hs), SCLSM=1 is required.
Figure 28-11. I
2
C Slave Behavioral Diagram (SCLSM=1)
S
S3
ADDRESS
S2
R
W
DATA A/A
DATA
P
S2
Sr
S3
P
S2
Sr
S3
S
W
S
W
S
W
A/A
S
W
Interrupt on STOP
Condition Enabled
S1
S
W
Software interaction
The master provides data
on the bus
Addressed slave provides
data on the bus
A/A
A/A
PREC INTERRUPT
AMATCH INTERRUPT
(+ DRDY INTERRUPT in Master Read mode)
DRDY INTERRUPT
28.6.2.5.1 Receiving Address Packets (SCLSM=0)
When CTRLA.SCLSM=0, the I2C slave stretches the SCL line according to Figure 28-10. When the I
2
C
slave is properly configured, it will wait for a start condition.
When a start condition is detected, the successive address packet will be received and checked by the
address match logic. If the received address is not a match, the packet will be rejected, and the I
2
C slave
will wait for a new start condition. If the received address is a match, the Address Match bit in the
Interrupt Flag register (INTFLAG.AMATCH) will be set.
SCL will be stretched until the I
2
C slave clears INTFLAG.AMATCH. As the I
2
C slave holds the clock by
forcing SCL low, the software has unlimited time to respond.
The direction of a transaction is determined by reading the Read / Write Direction bit in the Status register
(STATUS.DIR). This bit will be updated only when a valid address packet is received.
If the Transmit Collision bit in the Status register (STATUS.COLL) is set, this indicates that the last packet
addressed to the I
2
C slave had a packet collision. A collision causes the SDA and SCL lines to be
released without any notification to software. Therefore, the next AMATCH interrupt is the first indication
of the previous packet’s collision. Collisions are intended to follow the SMBus Address Resolution
Protocol (ARP).
After the address packet has been received from the I
2
C master, one of two cases will arise based on
transfer direction.
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 562