Datasheet

Figure 28-9. 10-bit Address Transmission for a Read Transaction
S AW
addr[7:0]
A
11110 addr[9:8]
Sr AR
1
S
W
11110 addr[9:8]
MB INTERRUPT
This implies the following procedure for a 10-bit read operation:
1. Write the 10-bit address to ADDR.ADDR[10:1]. ADDR.TENBITEN must be '1', the direction bit
(ADDR.ADDR[0]) must be '0' (can be written simultaneously with ADDR).
2. Once the Master on Bus interrupt is asserted, Write ADDR[7:0] register to '11110 address[9:8]
1'. ADDR.TENBITEN must be cleared (can be written simultaneously with ADDR).
3. Proceed to transmit data.
28.6.2.5 I
2
C Slave Operation
The I
2
C slave is byte-oriented and interrupt-based. The number of interrupts generated is kept at a
minimum by automatic handling of most events. The software driver complexity and code size are
reduced by auto-triggering of operations, and a special smart mode, which can be enabled by the Smart
Mode Enable bit in the Control A register (CTRLA.SMEN).
The I
2
C slave has two interrupt strategies.
When SCL Stretch Mode bit (CTRLA.SCLSM) is '0', SCL is stretched before or after the acknowledge bit.
In this mode, the I
2
C slave operates according to I
2
C Slave Behavioral Diagram (SCLSM=0). The circles
labelled "Sn" (S1, S2..) indicate the nodes the bus logic can jump to, based on software or hardware
interaction.
This diagram is used as reference for the description of the I
2
C slave operation throughout the document.
Figure 28-10. I
2
C Slave Behavioral Diagram (SCLSM=0)
S
S3
ADDRESS
S2
A
S1
R
W
DATA A/A
DATA
P
S2
Sr
S3
P
S2
Sr
S3
A
S
W
S
W
S
W
S
W
A
A/A
A
S1
S
W
Interrupt on STOP
Condition Enabled
S1
S
W
Software interaction
The master provides data
on the bus
Addressed slave provides
data on the bus
AMATCH INTERRUPT DRDY INTERRUPT
PREC INTERRUPT
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 561