Datasheet

28.6.2.4.4 Receiving Data Packets (SCLSM=0)
When INTFLAG.SB is set, the I
2
C master will already have received one data packet. The I
2
C master
must respond by sending either an ACK or NACK. Sending a NACK may be unsuccessful when
arbitration is lost during the transmission. In this case, a lost arbitration will prevent setting INTFLAG.SB.
Instead, INTFLAG.MB will indicate a change in arbitration. Handling of lost arbitration is the same as for
data bit transmission.
28.6.2.4.5 Receiving Data Packets (SCLSM=1)
When INTFLAG.SB is set, the I
2
C master will already have received one data packet and transmitted an
ACK or NACK, depending on CTRLB.ACKACT. At this point, CTRLB.ACKACT must be set to the correct
value for the next ACK bit, and the transaction can continue by reading DATA and issuing a command if
not in the smart mode.
28.6.2.4.6 High-Speed Mode
High-speed transfers are a multi-step process, see High Speed Transfer.
First, a master code (0b00001nnn, where 'nnn' is a unique master code) is transmitted in Full-speed
mode, followed by a NACK since no slaveshould acknowledge. Arbitration is performed only during the
Full-speed Master Code phase. The master code is transmitted by writing the master code to the address
register (ADDR.ADDR) and writing the high-speed bit (ADDR.HS) to '0'.
After the master code and NACK have been transmitted, the master write interrupt will be asserted. In the
meanwhile, the slave address can be written to the ADDR.ADDR register together with ADDR.HS=1.
Now in High-speed mode, the master will generate a repeated start, followed by the slave address with
RW-direction. The bus will remain in High-speed mode until a stop is generated. If a repeated start is
desired, the ADDR.HS bit must again be written to '1', along with the new address ADDR.ADDR to be
transmitted.
Figure 28-8. High Speed Transfer
S
A
A/A
Sr
PA DATA
N Data Packets
Master Code
R/W
ADDRESS
Sr
ADDRESS
Hs-mode continues
F/S-mode
Hs-mode
F/S-mode
Transmitting in High-speed mode requires the I
2
C master to be configured in High-speed mode
(CTRLA.SPEED=0x2) and the SCL clock stretch mode (CTRLA.SCLSM) bit set to '1'.
28.6.2.4.7 10-Bit Addressing
When 10-bit addressing is enabled by the Ten Bit Addressing Enable bit in the Address register
(ADDR.TENBITEN=1) and the Address bit field ADDR.ADDR is written, the two address bytes will be
transmitted, see 10-bit Address Transmission for a Read Transaction. The addressed slave
acknowledges the two address bytes, and the transaction continues. Regardless of whether the
transaction is a read or write, the master must start by sending the 10-bit address with the direction bit
(ADDR.ADDR[0]) being zero.
If the master receives a NACK after the first byte, the write interrupt flag will be raised and the
STATUS.RXNACK bit will be set. If the first byte is acknowledged by one or more slaves, then the master
will proceed to transmit the second address byte and the master will first see the write interrupt flag after
the second byte is transmitted. If the transaction direction is read-from-slave, the 10-bit address
transmission must be followed by a repeated start and the first 7 bits of the address with the read/write bit
equal to '1'.
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 560