Datasheet

Note: The I
2
C standard Fm+ (Fast-mode plus) requires a nominal high to low SCL ratio of 1:2, and
BAUD should be set accordingly. At a minimum, BAUD.BAUD and/or BAUD.BAUDLOW must be non-
zero.
Startup Timing The minimum time between SDA transition and SCL rising edge is 6 APB cycles when
the DATA register is written in smart mode. If a greater startup time is required due to long rise times, the
time between DATA write and IF clear must be controlled by software.
Note: When timing is controlled by user, the Smart Mode cannot be enabled.
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37. Electrical Characteristics
Master Clock Generation (High-Speed Mode)
For I
2
C Hs transfers, there is no SCL synchronization. Instead, the SCL frequency is determined by the
GCLK_SERCOMx_CORE frequency (f
GCLK
) and the High-Speed Baud setting in the Baud register
(BAUD.HSBAUD). When BAUD.HSBAUDLOW=0, the HSBAUD value will determine both SCL high and
SCL low. In this case the following formula determines the SCL frequency.

SCL
=

GCLK
2 + 2   
When HSBAUDLOW is non-zero, the following formula determines the SCL frequency.

SCL
=

GCLK
2 +   + 
Note: The I
2
C standard Hs (High-speed) requires a nominal high to low SCL ratio of 1:2, and HSBAUD
should be set accordingly. At a minimum, BAUD.HSBAUD and/or BAUD.HSBAUDLOW must be non-
zero.
28.6.2.4.2 Transmitting Address Packets
The I
2
C master starts a bus transaction by writing the I
2
C slave address to ADDR.ADDR and the direction
bit, as described in 28.6.1 Principle of Operation. If the bus is busy, the I
2
C master will wait until the bus
becomes idle before continuing the operation. When the bus is idle, the I
2
C master will issue a start
condition on the bus. The I
2
C master will then transmit an address packet using the address written to
ADDR.ADDR. After the address packet has been transmitted by the I
2
C master, one of four cases will
arise according to arbitration and transfer direction.
Case 1: Arbitration lost or bus error during address packet transmission
If arbitration was lost during transmission of the address packet, the Master on Bus bit in the Interrupt
Flag Status and Clear register (INTFLAG.MB) and the Arbitration Lost bit in the Status register
(STATUS.ARBLOST) are both set. Serial data output to SDA is disabled, and the SCL is released, which
disables clock stretching. In effect the I
2
C master is no longer allowed to execute any operation on the
bus until the bus is idle again. A bus error will behave similarly to the arbitration lost condition. In this
case, the MB interrupt flag and Master Bus Error bit in the Status register (STATUS.BUSERR) are both
set in addition to STATUS.ARBLOST.
The Master Received Not Acknowledge bit in the Status register (STATUS.RXNACK) will always contain
the last successfully received acknowledge or not acknowledge indication.
In this case, software will typically inform the application code of the condition and then clear the interrupt
flag before exiting the interrupt routine. No other flags have to be cleared at this moment, because all
flags will be cleared automatically the next time the ADDR.ADDR register is written.
Case 2: Address packet transmit complete – No ACK received
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 558