Datasheet

Figure 28-7. SCL Timing
TSU;STO THD;STA
TBUF
TFALL
TLOW
TRISE
THIGH
SCL
SDA
P S
TSU;STA
Sr
The following parameters are timed using the SCL low time period T
LOW
. This comes from the Master
Baud Rate Low bit group in the Baud Rate register (BAUD.BAUDLOW). When BAUD.BAUDLOW=0, or
the Master Baud Rate bit group in the Baud Rate register (BAUD.BAUD) determines it.
• T
LOW
– Low period of SCL clock
• T
SU;STO
– Set-up time for stop condition
• T
BUF
– Bus free time between stop and start conditions
• T
HD;STA
– Hold time (repeated) start condition
• T
SU;STA
– Set-up time for repeated start condition
• T
HIGH
is timed using the SCL high time count from BAUD.BAUD
• T
RISE
is determined by the bus impedance; for internal pull-ups. Refer to Electrical Characteristics.
• T
FALL
is determined by the open-drain current limit and bus impedance; can typically be regarded
as zero. Refer to Electrical Characteristics for details.
The SCL frequency is given by:

SCL
=
1

LOW
+ 
HIGH
+ 
RISE
When BAUD.BAUDLOW is zero, the BAUD.BAUD value is used to time both SCL high and SCL low. In
this case the following formula will give the SCL frequency:

SCL
=

GCLK
10 + 2 + 
GCLK
 
RISE
When BAUD.BAUDLOW is non-zero, the following formula determines the SCL frequency:

SCL
=

GCLK
10 +  +  + 
GCLK
 
RISE
The following formulas can determine the SCL T
LOW
and T
HIGH
times:

LOW
=
 + 5

GCLK

HIGH
=
 + 5

GCLK
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 557