Datasheet

Figure 28-6. I
2
C Master Behavioral Diagram (SCLSM=1)
IDLE S BUSYBUSY P
Sr
P
M3
M3
M2
M2
M1
M1
R DATA
W
A/ADATA
APPLICATION
SW
SW
Sr
P
M3
M2
BUSY
M4
SW
A/A
M4
A
IDLE
IDLE
Master Bus INTERRUPT + SCL HOLD
SW
SW
SW
BUSYR/W
A
A
R/W
BUSY
M4
SW
Software interaction
The master provides data on the bus
Addressed slave provides data on the bus
Slave Bus INTERRUPT + SCL HOLD
Wait for
IDLE
ADDRESS
28.6.2.4.1 Master Clock Generation
The SERCOM peripheral supports several I
2
C bidirectional modes:
• Standard mode (Sm) up to 100kHz
• Fast mode (Fm) up to 400kHz
• Fast mode Plus (Fm+) up to 1MHz
• High-speed mode (Hs) up to 3.4MHz
The Master clock configuration for Sm, Fm, and Fm+ are described in Clock Generation (Standard-Mode,
Fast-Mode, and Fast-Mode Plus). For Hs, refer to Master Clock Generation (High-Speed Mode).
Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus)
In I
2
C Sm, Fm, and Fm+ mode, the Master clock (SCL) frequency is determined as described in this
section:
The low (T
LOW
) and high (T
HIGH
) times are determined by the Baud Rate register (BAUD), while the rise
(T
RISE
) and fall (T
FALL
) times are determined by the bus topology. Because of the wired-AND logic of the
bus, T
FALL
will be considered as part of T
LOW
. Likewise, T
RISE
will be in a state between T
LOW
and T
HIGH
until a high state has been detected.
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 556