Datasheet

28.6.2.4 I
2
C Master Operation
The I
2
C master is byte-oriented and interrupt based. The number of interrupts generated is kept at a
minimum by automatic handling of most incidents. The software driver complexity and code size are
reduced by auto-triggering of operations, and a special smart mode, which can be enabled by the Smart
Mode Enable bit in the Control A register (CTRLA.SMEN).
The I
2
C master has two interrupt strategies.
When SCL Stretch Mode (CTRLA.SCLSM) is '0', SCL is stretched before or after the acknowledge bit . In
this mode the I
2
C master operates according to Master Behavioral Diagram (SCLSM=0). The circles
labelled "Mn" (M1, M2..) indicate the nodes the bus logic can jump to, based on software or hardware
interaction.
This diagram is used as reference for the description of the I
2
C master operation throughout the
document.
Figure 28-5. I
2
C Master Behavioral Diagram (SCLSM=0)
IDLE S BUSYBUSY P
Sr
P
M3
M3
M2
M2
M1
M1
R DATA
Wait for
IDLE
ADDRESS
W
A/ADATA
APPLICATION
SW
SW
Sr
P
M3
M2
BUSY
M4
A
SW
A/A
A/A
A/A
M4
A
IDLE
IDLE
Slave Bus INTERRUPT + SCL HOLD
Master Bus INTERRUPT + SCL HOLD
SW
SW
SW
BUSYR/W
SW
Software interaction
A
A
R/W
BUSY
M4
The master provides data on the bus
Addressed slave provides data on the bus
In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit, as in Master
Behavioral Diagram (SCLSM=1). This strategy can be used when it is not necessary to check DATA
before acknowledging.
Note: I
2
C High-speed (Hs) mode requires CTRLA.SCLSM=1.
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 555