Datasheet

ManualsBrandsMicrochip ManualsARM MicrocontrollersARM® Cortex® M0+ SAM Microcontroller 32bit 256KB TQFP

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Figure 28-4. Bus State Diagram

RESET

Write ADDR to generate

Start Condition

IDLE

(0b01)

Start Condition

BUSY

(0b11)

Timeout or Stop Condition

UNKNOWN

(0b00)

OWNER

(0b10)

Lost Arbitration

Repeated

Start Condition

Write ADDR to generate

Repeated Start Condition

Stop Condition

Timeout or Stop Condition

The bus state machine is active when the I

C master is enabled.

After the I

C master has been enabled, the bus state is UNKNOWN (0b00). From the UNKNOWN state,

the bus will transition to IDLE (0b01) by either:

• Forcing by writing 0b01 to STATUS.BUSSTATE

• A stop condition is detected on the bus

• If the inactive bus time-out is configured for SMBus compatibility (CTRLA.INACTOUT) and a time-

out occurs.

Note: Once a known bus state is established, the bus state logic will not re-enter the UNKNOWN state.

When the bus is IDLE it is ready for a new transaction. If a start condition is issued on the bus by another

C master in a multi-master setup, the bus becomes BUSY (0b11). The bus will re-enter IDLE either

when a stop condition is detected, or when a time-out occurs (inactive bus time-out needs to be

configured).

If a start condition is generated internally by writing the Address bit group in the Address register

(ADDR.ADDR) while IDLE, the OWNER state (0b10) is entered. If the complete transaction was

performed without interference, i.e., arbitration was not lost, the I

C master can issue a stop condition,

which will change the bus state back to IDLE.

However, if a packet collision is detected while in OWNER state, the arbitration is assumed lost and the

bus state becomes BUSY until a stop condition is detected. A repeated start condition will change the bus

state only if arbitration is lost while issuing a repeated start.

Note: Violating the protocol may cause the I

C to hang. If this happens it is possible to recover from this

state by a software reset (CTRLA.SWRST='1').