Datasheet

PAC Write-Protection is not available for the following registers:

• Interrupt Flag Clear and Status register (INTFLAG)

• Status register (STATUS)

• Data register (DATA)

• Address register (ADDR)

Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual

Write-protection does not apply to accesses through an external debugger.

Related Links

11.6 PAC - Peripheral Access Controller

28.5.9 Analog Connections

Not applicable.

28.6 Functional Description

28.6.1 Principle of Operation

The I

C interface uses two physical lines for communication:

• Serial Data Line (SDA) for data transfer

• Serial Clock Line (SCL) for the bus clock

A transaction starts with the I

C master sending the start condition, followed by a 7-bit address and a

direction bit (read or write to/from the slave).

The addressed I

C slave will then acknowledge (ACK) the address, and data packet transactions can

begin. Every 9-bit data packet consists of 8 data bits followed by a one-bit reply indicating whether the

data was acknowledged or not.

If a data packet is not acknowledged (NACK), whether by the I

C slave or master, the I

C master takes

action by either terminating the transaction by sending the stop condition, or by sending a repeated start

to transfer more data.

The figure below illustrates the possible transaction formats and Transaction Diagram Symbols explains

the transaction symbols. These symbols will be used in the following descriptions.

SAM D21 Family

SERCOM I2C – Inter-Integrated Circuit

Datasheet Complete

DS40001882D-page 551