Datasheet

28.5.2 Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. The
interrupts can wake up the device from sleep modes.
Related Links
16. PM – Power Manager
28.5.3 Clocks
The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Power Manager.
Refer to Peripheral Clock Masking for details and default status of this clock.
Two generic clocks are used by SERCOM, GCLK_SERCOMx_CORE and GCLK_SERCOM_SLOW. The
core clock (GCLK_SERCOMx_CORE) can clock the I
2
C when working as a master. The slow clock
(GCLK_SERCOM_SLOW) is required only for certain functions, e.g. SMBus timing. These two clocks
must be configured and enabled in the Generic Clock Controller (GCLK) before using the I
2
C.
These generic clocks are asynchronous to the bus clock (CLK_SERCOMx_APB). Due to this
asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to
28.6.6 Synchronization for further details.
Related Links
15. GCLK - Generic Clock Controller
16. PM – Power Manager
16.6.2.6 Peripheral Clock Masking
28.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with
this peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for
details.
Related Links
20. DMAC – Direct Memory Access Controller
28.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this
peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt
Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
28.5.6 Events
Not applicable.
28.5.7 Debug Operation
When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is
configured to require periodical service by the CPU through interrupts or similar, improper operation or
data loss may result during debugging. This peripheral can be forced to halt operation during debugging -
refer to the Debug Control (DBGCTRL) register for details.
28.5.8 Register Access Protection
Registers with write-access can be write-protected optionally by the peripheral access controller (PAC).
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 550