Datasheet

28. SERCOM I
2
C – Inter-Integrated Circuit
28.1 Overview
The inter-integrated circuit ( I
2
C) interface is one of the available modes in the serial communication
interface (SERCOM).
The I
2
C interface uses the SERCOM transmitter and receiver configured as shown in Figure 28-1. Labels
in capital letters are registers accessible by the CPU, while lowercase labels are internal to the SERCOM.
A SERCOM instance can be configured to be either an I
2
C master or an I
2
C slave. Both master and slave
have an interface containing a shift register, a transmit buffer and a receive buffer. In addition, the I
2
C
master uses the SERCOM baud-rate generator, while the I
2
C slave uses the SERCOM address match
logic.
Related Links
25. SERCOM – Serial Communication Interface
28.2 Features
SERCOM I
2
C includes the following features:
• Master or slave operation
• Can be used with DMA
• Philips I
2
C compatible
• SMBus
™
compatible
• PMBus compatible
• Support of 100kHz and 400kHz, 1MHz and 3.4MHz I
2
C mode
• Up to 16-bytes internal FIFO
• 4-Wire operation supported
• Physical interface includes:
– Slew-rate limited outputs
– Filtered inputs
• Slave operation:
– Operation in all sleep modes
– Wake-up on address match
– 7-bit and 10-bit Address match in hardware for:
– • Unique address and/or 7-bit general call address
• Address range
• Two unique addresses can be used with DMA
Related Links
25.2 Features
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 548