Datasheet

27.8.4 Interrupt Enable Clear
Name: INTENCLR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 7 6 5 4 3 2 1 0
ERROR SSL RXC TXC DRE
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 – ERROR Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 3 – SSL Slave Select Low Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Slave Select Low Interrupt Enable bit, which disables the Slave Select
Low interrupt.
Value Description
0
Slave Select Low interrupt is disabled.
1
Slave Select Low interrupt is enabled.
Bit 2 – RXC Receive Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive
Complete interrupt.
Value Description
0
Receive Complete interrupt is disabled.
1
Receive Complete interrupt is enabled.
Bit 1 – TXC Transmit Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Transmit Complete Interrupt Enable bit, which disable the Transmit
Complete interrupt.
Value Description
0
Transmit Complete interrupt is disabled.
1
Transmit Complete interrupt is enabled.
SAM D21 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 534