Datasheet

Writing '1' to CTRLB.RXEN when the SPI is enabled will set SYNCBUSY.CTRLB, which will remain set

until the receiver is enabled, and CTRLB.RXEN will read back as '1'.

This bit is not enable-protected.

Value Description

The receiver is disabled or being enabled.

The receiver is enabled or it will be enabled when SPI is enabled.

Bits 15:14 – AMODE[1:0] Address Mode

These bits set the slave addressing mode when the frame format (CTRLA.FORM) with address is used.

They are unused in master mode.

AMODE[1:0] Name Description

0x0 MASK ADDRMASK is used as a mask to the ADDR register

0x1 2_ADDRS The slave responds to the two unique addresses in ADDR and ADDRMASK

0x2 RANGE The slave responds to the range of addresses between and including ADDR

and ADDRMASK. ADDR is the upper limit

0x3 - Reserved

Bit 13 – MSSEN Master Slave Select Enable

This bit enables hardware slave select (SS) control.

Value Description

Hardware SS control is disabled.

Hardware SS control is enabled.

Bit 9 – SSDE Slave Select Low Detect Enable

This bit enables wake up when the slave select (SS) pin transitions from high to low.

Value Description

SS low detector is disabled.

SS low detector is enabled.

Bit 6 – PLOADEN Slave Data Preload Enable

Setting this bit will enable preloading of the slave shift register when there is no transfer in progress. If the

SS line is high when DATA is written, it will be transferred immediately to the shift register.

Bits 2:0 – CHSIZE[2:0] Character Size

CHSIZE[2:0] Name Description

0x0 8BIT 8 bits

0x1 9BIT 9 bits

0x2-0x7 - Reserved

SAM D21 Family

SERCOM SPI – SERCOM Serial Peripheral Interface

Datasheet Complete

DS40001882D-page 532