Datasheet

27.8.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
FIFOCLR[1:0] RXEN
Access
R/W R/W R/W
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8
AMODE[1:0] MSSEN SSDE
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PLOADEN CHSIZE[2:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bits 23:22 – FIFOCLR[1:0] FIFO Clear
When these bits are set, the corresponding FIFO will be cleared. The bits will automatically clear when
SYNCBUSY.CTRLB = 0.
These bits are not enable-protected.
FIFOCLR[1:0] Name Description
0x0 NONE No action
0x1 TXFIFO Clear TX FIFO
0x2 RXFIFO Clear RX FIFO
0x3 BOTH Clear both TX/RX FIFO
Bit 17 – RXEN Receiver Enable
Writing '0' to this bit will disable the SPI receiver immediately. The receive buffer will be flushed, data from
ongoing receptions will be lost and STATUS.BUFOVF will be cleared.
Writing '1' to CTRLB.RXEN when the SPI is disabled will set CTRLB.RXEN immediately. When the SPI is
enabled, CTRLB.RXEN will be cleared, SYNCBUSY.CTRLB will be set and remain set until the receiver is
enabled. When the receiver is enabled CTRLB.RXEN will read back as '1'.
SAM D21 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 531