Datasheet

Figure 11-1. APB Write Access.
T0 T1 T2 T3
Addr 1
Data 1
PADDR
PWRITE
PCLK
PSEL
PENABLE
PWDATA
PREADY
T0 T1 T2 T3
Addr 1
Data 1
PADDR
PWRITE
PCLK
PSEL
PENABLE
PWDATA
PREADY
T4 T5
Wait statesNo wait states
Figure 11-2. APB Read Access.
T0 T1 T2 T3
Addr 1
Data 1
PADDR
PWRITE
PCLK
PSEL
PENABLE
PRDATA
PREADY
T0 T1 T2 T3
Addr 1
Data 1
PADDR
PWRITE
PCLK
PSEL
PENABLE
PRDATA
PREADY
T4 T5
Wait statesNo wait states
Related Links
16. PM – Power Manager
9. Product Mapping
11.6 PAC - Peripheral Access Controller
11.6.1 Overview
One PAC is associated with each AHB-APB bridge and the PAC can provide write protection for registers
of each peripheral connected on the same bridge.
The PAC peripheral bus clock (CLK_PACx_APB) can be enabled and disabled in the Power Manager.
CLK_PAC0_APB and CLK_PAC1_APB are enabled are reset. CLK_PAC2_APB is disabled at reset.
Refer to PM – Power Manager for details. The PAC will continue to operate in any Sleep mode where the
selected clock source is running. Write-protection does not apply for debugger access. When the
SAM D21 Family
Processor And Architecture
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 53