Datasheet

DOPO DO SCK Slave SS Master SS
0x0 PAD[0] PAD[1] PAD[2] System configuration
0x1 PAD[2] PAD[3] PAD[1] System configuration
0x2 PAD[3] PAD[1] PAD[2] System configuration
0x3 PAD[0] PAD[3] PAD[1] System configuration
Bit 8 – IBON Immediate Buffer Overflow Notification
This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is set when a buffer overflow
occurs.
This bit is not synchronized.
Value Description
0
STATUS.BUFOVF is set when it occurs in the data stream.
1
STATUS.BUFOVF is set immediately upon buffer overflow.
Bit 7 – RUNSTDBY Run In Standby
This bit defines the functionality in standby sleep mode.
These bits are not synchronized.
RUNSTDBY Slave Master
0x0 Disabled. All reception is dropped,
including the ongoing transaction.
Generic clock is disabled when ongoing
transaction is finished. All interrupts can wake
up the device.
0x1 Ongoing transaction continues, wake on
Receive Complete interrupt.
Generic clock is enabled while in sleep modes.
All interrupts can wake up the device.
Bits 4:2 – MODE[2:0] Operating Mode
These bits must be written to 0x2 or 0x3 to select the SPI serial communication interface of the
SERCOM.
0x2: SPI slave operation
0x3: SPI master operation
These bits are not synchronized.
Bit 1 – ENABLE Enable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/
disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable
Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is
cleared when the operation is complete.
This bit is not enable-protected.
Value Description
0
The peripheral is disabled or being disabled.
1
The peripheral is enabled or being enabled.
SAM D21 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 529