Datasheet

27.8.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit 31 30 29 28 27 26 25 24
DORD CPOL CPHA FORM[3:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DIPO[1:0] DOPO[1:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
IBON
Access
R/W
Reset 0
Bit 7 6 5 4 3 2 1 0
RUNSTDBY MODE[2:0] ENABLE SWRST
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 30 – DORD Data Order
This bit selects the data order when a character is shifted out from the shift register.
This bit is not synchronized.
Value Description
0
MSB is transferred first.
1
LSB is transferred first.
Bit 29 – CPOL Clock Polarity
In combination with the Clock Phase bit (CPHA), this bit determines the SPI transfer mode.
This bit is not synchronized.
Value Description
0
SCK is low when idle. The leading edge of a clock cycle is a rising edge, while the trailing
edge is a falling edge.
1
SCK is high when idle. The leading edge of a clock cycle is a falling edge, while the trailing
edge is a rising edge.
Bit 28 – CPHA Clock Phase
In combination with the Clock Polarity bit (CPOL), this bit determines the SPI transfer mode.
SAM D21 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 527