Datasheet

• Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty or if at least
TXTRHOLD data locations are empty in the TX FIFO, when FIFO operation is enabled. The
request is cleared when DATA is written.
27.6.4.2 Interrupts
The SPI has the following interrupt sources. These are asynchronous interrupts, and can wake up the
device from any sleep mode:
• Data Register Empty (DRE)
• Receive Complete (RXC)
• Transmit Complete (TXC)
• Slave Select Low (SSL)
• Error (ERROR)
Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) will be set when the interrupt condition is met. Each interrupt can be individually
enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and
disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).
An interrupt request is generated when the interrupt flag is set and if the corresponding interrupt is
enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is
disabled, or the SPI is reset. For details on clearing interrupt flags, refer to the INTFLAG register
description.
The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally
enabled for interrupt requests. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
27.6.4.3 Events
Not applicable.
27.6.5 Sleep Mode Operation
The behavior in sleep mode is depending on the master/slave configuration and the Run In Standby bit in
the Control A register (CTRLA.RUNSTDBY):
• Master operation, CTRLA.RUNSTDBY=1: The peripheral clock GCLK_SERCOM_CORE will
continue to run in idle sleep mode and in standby sleep mode. Any interrupt can wake up the
device.
• Master operation, CTRLA.RUNSTDBY=0: GLK_SERCOMx_CORE will be disabled after the
ongoing transaction is finished. Any interrupt can wake up the device.
• Slave operation, CTRLA.RUNSTDBY=1: The Receive Complete interrupt can wake up the device.
• Slave operation, CTRLA.RUNSTDBY=0: All reception will be dropped, including the ongoing
transaction.
27.6.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
The following bits are synchronized when written:
• Software Reset bit in the CTRLA register (CTRLA.SWRST)
SAM D21 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 523