Datasheet

27.6.4 DMA, Interrupts, and Events
Table 27-4. Module Request for SERCOM SPI
Condition Request
DMA Interrupt Event
Data Register Empty (DRE) Yes
(request cleared when data is written)
Yes NA
Receive Complete (RXC) Yes
(request cleared when data is read)
Yes
Transmit Complete (TXC) NA Yes
Slave Select low (SSL) NA Yes
Error (ERROR) NA Yes
Table 27-5. Module Request for SERCOM SPI
Condition Request
DMA Interrupt Event
Standard (DRE): Data Register Empty
FIFO (DRE): at least TXTRHOLD locations in TX FIFO are
empty
Yes
(request cleared when
data is written)
Yes NA
Standard (RXC): Receive Complete
FIFO (RXC): at least RXTRHOLD data available in RX
FIFO, or a last word available and length frame reception
completed.
Yes
(request cleared when
data is read)
Yes
Standard (TXC): Transmit Complete
FIFO (TXC): Transmit Complete and TX FIFO is empty
NA Yes
Slave Select low (SSL) NA Yes
Error (ERROR) NA Yes
27.6.4.1 DMA Operation
The SPI generates the following DMA requests:
• Data received (RX): The request is set when data is available in the receive FIFO. The request is
cleared when DATA is read.
• Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is
cleared when DATA is written.
• Data received (RX): The request is set when data is available in the receive FIFO or if at least
RXTRHOLD data are available in the RX FIFO when FIFO operation is enabled. The request is
cleared when DATA is read.
SAM D21 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
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