Datasheet

The interrupts and DMA triggers are generated according to FIFO threshold settings in Control C register
(CTRLC.TXTRHOLD, CTRLC.RXTRHOLD).
The Data Register Empty interrupt flag, and the DMA TX trigger respectivly, are generated when the
available place in the TX FIFO is equal or higher than the threshold value defined by the
CTRLC.TXTRHOLD settings. The Transfer complete interrupt is generated when the TX FIFO is empty
and the last bit is shifted out.
The Receive Complete interrupt flag, and the DMA RX trigger respectivly, are generated when the
number of bytes present in the RX FIFO equals or is higher than the threshold value defined by the
CTRLC.RXTRHOLD settings. The ERROR interrupt flag is generated when both RX shifter and the RX
FIFO are full.
The FIFO is fully accessible if the SERCOM is halted, by writting the corresponding CPU FIFO pointer in
the FIFOPTR register. The RX or TX FIFO can be individually cleared, by setting the respective FIFO
Clear bit in the Control B register (CTRLB.FIFOCLR). The FIFO Clear must be written before data
transfer begins. Writing the FIFO Clear bits while a frame is in progress will produce unpredicatable
results.
27.6.3.7.1 Pointer Operation in Master Mode
In Master mode, the transmit / receive sequence is started by the CPU writing one or more transmit words
into the TX FIFO. The CPUWRPTR is incremented by 1 every time the CPU writes a word to the memory
array. As soon as the CPUWRPTR becomes not-equal to SPIRDPTR (FIFOSPACE.TXSPACE != 0), the
SPI transmits the data pointed to by the SPIRDPTR through MOSI. When a complete word is shifted in,
the SPIRDPTR is compared to CPUWRPTR. If they are not equal, SPIRDPTR is incremented, another
byte / word is shifted in/out, and so on. When the CPU completes a read from the RX FIFO location
(FIFOSPACE.RXSPACE != 0), the CPURDPTR pointer is incremented. When both RX shifter and RX
FIFO are full, the Buffer Overflow status bit is set (STATUS.BUFOVF) and optional ERROR interrupt is
generated. The module will not respond to SCK transitions while BUFOVF is ‘1’, effectively disabling the
module until software reads DATA register.
All pointers increment to their maximum value, dictated by CTRLC.DATA32B bit, and then rolls over to ‘0’.
CPURDPTR will not increment past SPIWRPTR. In other words, if CPURDPTR = SPIWRPTR, and the
CPU attempts another read, the pointer will stay at the value of SPIWRPTR.
27.6.3.7.2 Pointer Operation in Slave Mode
In Slave mode, the transmit / receive sequence is started by the SPI receiving an SCK clock pulse. As
soon as an SCK pulse is received, the SPI transmits the data pointed to by the SPIRDPTR. When a
complete data is shifted in, the SPIRDPTR / SPIWRPTR are incremented, another data are shifted in/out,
and so on. The newly received data is written to the RX FIFO location pointed to by SPIWRPTR. The
CPUWRPTR is incremented by one every time the CPU writes a new data to the TX FIFO memory array.
If the CPUWRPTR is pointing to location n, and SPIWRPTR is pointing to location n, and a wrap is not
detected, the CPUWRPTR will auto-increment to SPIWRPTR, to keep up with SPIWRPTR. This is so that
the next data to be transmitted will be placed in the correct position in the storage element. The CPU can
read data from RX FIFO as long as FIFOSPACE.RXSPACE != 0. When both RX shifter and RX FIFO are
full, the Buffer Overflow status bit is set (STATUS.BUFOVF) and optional ERROR interrupt is generated.
The module will not respond to SCK transitions while BUFOVF is ‘1’, effectively disabling the module until
software reads RX FIFO. All pointers increment to their maximum value, dictated by CTRLC.DATA32B
bit, and then roll over to ‘0’. CPURDPTR will not increment past SPIWRPTR. In other words, if
CPURDPTR = SPIWRPTR, and the CPU attempts another read, the pointer will stay at the value of
SPIWRPTR.
SAM D21 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 521