Datasheet
In Hardware Controlled SS, the time T is between one and two baud cycles depending on the SPI
transfer mode.
Figure 27-7. Hardware Controlled SS
_SS
SCK
T
T = 1 to 2 baud cycles
T
T
T
T
When CTRLB.MSSEN=0, the SS pin(s) is/are controlled by user software and normal GPIO.
27.6.3.6 Slave Select Low Detection
In slave mode, the SPI can wake the CPU when the slave select (SS) goes low. When the Slave Select
Low Detect is enabled (CTRLB.SSDE=1), a high-to-low transition will set the Slave Select Low interrupt
flag (INTFLAG.SSL) and the device will wake up if applicable.
27.6.3.7 FIFO Operation
The SPI embeds up to 16-bytes FIFO capability. The receive / transmit buffer is considered to have the
FIFO mode enabled when the FIFOEN bit in CTRLC register is set to a ‘1’ (CTRLC.FIFOEN = 1). By
default, the FIFO can act as a 16-by-8-bit array, or as a 4-by-32-bit array, depending on the setting of the
CTRLC.DATA32B bit.
The hardware around this array implements four pointers, called the CPU Write Pointer (CPUWRPTR),
the CPU Read Pointer (CPURDPTR), the SPI Write pointer (SPIWRPTR) and the SPI Read pointer
(SPIRDPTR). All of these pointers reset to ‘0’. The CPUWRPTR and CPURDPTR pointers are native to
the CPU clock domain, while the SPIWRPTR and SPIRDPTR are native to the SPI domain. The location
pointed to by the CPUWRPTR is the current TX FIFO. The location pointed to by the CPURDPTR
becomes the current RX FIFO. Writes to DATA register by the CPU will point to TX FIFO. Reads to DATA
register by the CPU will point to RX FIFO. The location pointed to by the SPIWRPTR / SPIRDPTR is
logically the current shift register. Physically, the receive (shift-in) portion of the shift register is a single
register located in the SCK clock domain, and the transmit (shift-out) portion is the buffer location pointed
to by the SPIRDPTR. When a full word / byte is clocked into the SPI shift register, it is copied into the
location pointed by SPIWRPTR.
Figure 27-8. FIFO Overview
RX FIFO
TX FIFO
DATA DATA
Shift Register
MOSIMISO
CPUWRPTR
CPURDPTR
SPIWRPTR
SPIRDPTR
TX FIFO
THRESHOLD
Interrupt /
DMA Req.
Interrupt /
DMA Req.
RX FIFO
THRESHOLD
SAM D21 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 520