Datasheet

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Value Name Description

10 MEDIUM Sensitive Latency

11 HIGH Critical Latency

If a master is configured with QoS level 0x00 or 0x01 there will be minimum one cycle latency for the

RAM access.

The priority order for concurrent accesses are decided by two factors. First the QoS level for the master

and then a static priority given by table nn-mm (table: SRAM port connection) where the lowest port ID

has the highest static priority.

The MTB has fixed QoS level 3 and the DSU has fixed QoS level 1.

The CPU QoS level can be written/read at address 0x41007110, bits [1:0]. Its reset value is 0x0.

Refer to different master QOSCTRL registers for configuring QoS for the other masters (USB, DMAC).

11.5 AHB-APB Bridge

The AHB-APB bridge is an AHB slave, providing an interface between the high-speed AHB domain and

the low-power APB domain. It is used to provide access to the programmable control registers of

peripherals.

AHB-APB bridge is based on AMBA APB Protocol Specification V2.0 (ref. as APB4) including:

• Wait state support

• Error reporting

• Transaction protection

• Sparse data transfer (byte, half-word and word)

Additional enhancements:

• Address and data cycles merged into a single cycle

• Sparse data transfer also apply to read access

to operate the AHB-APB bridge, the clock (CLK_HPBx_AHB) must be enabled. See PM – Power

Manager for details.

SAM D21 Family

Processor And Architecture

Datasheet Complete

DS40001882D-page 52