Datasheet

In SPI slave operation (CTRLA.MODE is 0x2), the clock is provided by an external master on the SCK
pin. This clock is used to directly clock the SPI shift register.
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25.6.2.3 Clock Generation – Baud-Rate Generator
25.6.2.3.1 Asynchronous Arithmetic Mode BAUD Value Selection
27.6.2.4 Data Register
The SPI Transmit Data register (TxDATA) and SPI Receive Data register (RxDATA) share the same I/O
address, referred to as the SPI Data register (DATA). Writing DATA register will update the Transmit Data
register. Reading the DATA register will return the contents of the Receive Data register.
27.6.2.5 SPI Transfer Modes
There are four combinations of SCK phase and polarity to transfer serial data. The SPI data transfer
modes are shown in SPI Transfer Modes (Table) and SPI Transfer Modes (Figure).
SCK phase is configured by the Clock Phase bit in the CTRLA register (CTRLA.CPHA). SCK polarity is
programmed by the Clock Polarity bit in the CTRLA register (CTRLA.CPOL). Data bits are shifted out and
latched in on opposite edges of the SCK signal. This ensures sufficient time for the data signals to
stabilize.
Table 27-3. SPI Transfer Modes
Mode CPOL CPHA Leading Edge Trailing Edge
0 0 0 Rising, sample Falling, setup
1 0 1 Rising, setup Falling, sample
2 1 0 Falling, sample Rising, setup
3 1 1 Falling, setup Rising, sample
Note:
Leading edge is the first clock edge in a clock cycle.
Trailing edge is the second clock edge in a clock cycle.
SAM D21 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 515