Datasheet

27.3 Block Diagram
Figure 27-1. Full-Duplex SPI Master Slave Interconnection
BAUD
baud rate generator
Tx DATA
shift register
rx buffer
Rx DATA
Master Slave
Tx DATA
shift register
rx buffer
Rx DATA
SCK
_SS
MISO
MOSI
ADDR/ADDRMASK
==
Address Match
27.4 Signal Description
Table 27-1. SERCOM SPI Signals
Signal Name Type Description
PAD[3:0] Digital I/O General SERCOM pins
One signal can be mapped to one of several pins.
Related Links
7. I/O Multiplexing and Considerations
27.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
27.5.1 I/O Lines
In order to use the SERCOM’s I/O lines, the I/O pins must be configured using the IO Pin Controller
(PORT).
When the SERCOM is configured for SPI operation, the SERCOM controls the direction and value of the
I/O pins according to the table below. Both PORT control bits PINCFGn.PULLEN and PINCFGn.DRVSTR
are still effective. If the receiver is disabled, the data input pin can be used for other purposes. In master
mode, the slave select line (SS) is hardware controlled when the Master Slave Select Enable bit in the
Control B register (CTRLB.MSSEN) is '1'.
Table 27-2. SPI Pin Configuration
Pin Master SPI Slave SPI
MOSI Output Input
MISO Input Output
SCK Output Input
SS Output (CTRLB.MSSEN=1) Input
SAM D21 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 511