Datasheet

27. SERCOM SPI – SERCOM Serial Peripheral Interface
27.1 Overview
The serial peripheral interface (SPI) is one of the available modes in the Serial Communication Interface
(SERCOM).
The SPI uses the SERCOM transmitter and receiver configured as shown in 27.3 Block Diagram. Each
side, master and slave, depicts a separate SPI containing a shift register, a transmit buffer and a two-level
receive buffer. In addition, the SPI master uses the SERCOM baud-rate generator, while the SPI slave
can use the SERCOM address match logic. Labels in capital letters are synchronous to
CLK_SERCOMx_APB and accessible by the CPU, while labels in lowercase letters are synchronous to
the SCK clock.
Related Links
25. SERCOM – Serial Communication Interface
27.2 Features
SERCOM SPI includes the following features:
• Full-duplex, four-wire interface (MISO, MOSI, SCK, SS)
• One-level transmit buffer, two-level receive buffer
• Supports all four SPI modes of operation
• Single data direction operation allows alternate function on MISO or MOSI pin
• Selectable LSB- or MSB-first data transfer
• Can be used with DMA
• Up to 16-bytes internal FIFO
• Master operation:
– Serial clock speed, f
SCK
=1/t
SCK
(1)
– 8-bit clock generator
– Hardware controlled SS
• Slave Operation:
– Serial clock speed, f
SCK
=1/t
SSCK
(1)
– Optional 8-bit address match operation
– Operation in all sleep modes
– Wake on SS transition
1. For t
SCK
and t
SSCK
values, refer to SPI Timing Characteristics.
Related Links
37.16.2 SERCOM in SPI Mode Timing
25. SERCOM – Serial Communication Interface
25.2 Features
SAM D21 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 510