Datasheet

Table 11-4. Bus Matrix Masters
Bus Matrix Masters Master ID
CM0+ - Cortex M0+ Processor 0
DSU - Device Service Unit 1
DMAC - Direct Memory Access Controller / Data Access 2
Table 11-5. Bus Matrix Slaves
Bus Matrix Slaves Slave ID
Internal Flash Memory 0
AHB-APB Bridge A 1
AHB-APB Bridge B 2
AHB-APB Bridge C 3
SRAM Port 4 - CM0+ Access 4
SRAM Port 5 - DMAC Data Access 5
SRAM Port 6 - DSU Access 6
Table 11-6. SRAM Port Connection
SRAM Port Connection Port ID Connection Type
MTB - Micro Trace Buffer 0 Direct
USB - Universal Serial Bus 1 Direct
DMAC - Direct Memory Access Controller - Write-Back Access 2 Direct
DMAC - Direct Memory Access Controller - Fetch Access 3 Direct
CM0+ - Cortex M0+ Processor 4 Bus Matrix
DMAC - Direct Memory Access Controller - Data Access 5 Bus Matrix
DSU - Device Service Unit 6 Bus Matrix
11.4.3 SRAM Quality of Service
To ensure that masters with latency requirements get sufficient priority when accessing RAM, the different
masters can be configured to have a given priority for different type of access.
The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any
access to the RAM the RAM also receives the QoS level. The QoS levels and their corresponding bit
values for the QoS level configuration is shown in Table. Quality of Service.
Table 11-7. Quality of Service
Value Name Description
00 DISABLE Background (no sensitive operation)
01 LOW Sensitive Bandwidth
SAM D21 Family
Processor And Architecture
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 51