Datasheet

26.8.10 Data
Name: DATA
Offset: 0x28
Reset: 0x0000
Property: -
Bit 15 14 13 12 11 10 9 8
DATA[8:8]
Access
R/W
Reset 0
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 8:0 – DATA[8:0] Data
Reading these bits will return the contents of the Receive Data register. The register should be read only
when the Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register
(INTFLAG.RXC) is set. The status bits in STATUS should be read before reading the DATA value in order
to get any corresponding error.
Writing these bits will write the Transmit Data register. This register should be written only when the Data
Register Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set.
SAM D21 Family
SERCOM USART
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 506