Datasheet

M0+ Technical Reference Manual. The MTB has 4 programmable registers to control the behavior of the
trace features:
• POSITION: Contains the trace write pointer and the wrap bit,
• MASTER: Contains the main trace enable bit and other trace control fields,
• FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits,
• BASE: Indicates where the SRAM is located in the processor memory map. This register is
provided to enable auto discovery of the MTB SRAM location, by a debug agent.
See the CoreSight MTB-M0+ Technical Reference Manual for a detailed description of these registers.
11.4 High-Speed Bus System
11.4.1 Features
High-Speed Bus Matrix has the following features:
• Symmetric crossbar bus switch implementation
• Allows concurrent accesses from different masters to different slaves
• 32-bit data bus
• Operation at a one-to-one clock frequency with the bus masters
11.4.2 Configuration
CM0+ 0
DSU 1
High-Speed Bus SLAVES
Internal Flash
0
AHB-APB Bridge A
1
AHB-APB Bridge B
2
AHB-APB Bridge C
3
MTB
Multi-Slave
MASTERS
USB
DMAC WB DMAC Fetch
CM0+
4
DMAC Data DSU
6
SRAM
DSU 1
MTB
USB
DMAC WB
DMAC Fetch
Priviledged SRAM-access
MASTERS
DSU 2
DMAC Data
4
5
0 1 2 3
65
SLAVE ID
SRAM PORT ID
MASTER ID
SAM D21 Family
Processor And Architecture
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 50