Datasheet

Bits 4:2 – MODE[2:0] Operating Mode

These bits select the USART serial communication interface of the SERCOM.

These bits are not synchronized.

Value Description

0x0

USART with external clock

0x1

USART with internal clock

Bit 1 – ENABLE Enable

Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/

disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable

Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set.

SYNCBUSY.ENABLE is cleared when the operation is complete.

This bit is not enable-protected.

Value Description

The peripheral is disabled or being disabled.

The peripheral is enabled or being enabled.

Bit 0 – SWRST Software Reset

Writing '0' to this bit has no effect.

Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the

SERCOM will be disabled.

Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same

write-operation will be discarded. Any register write access during the ongoing reset will result in an APB

error. Reading any register will return the reset value of the register.

Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete.

CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.

This bit is not enable-protected.

Value Description

There is no reset operation ongoing.

The reset operation is ongoing.

SAM D21 Family

SERCOM USART

Datasheet Complete

DS40001882D-page 490