Datasheet

This bit is not synchronized.
TXPO TxD Pin Location XCK Pin Location (When
Applicable)
RTS CTS
0x0 SERCOM PAD[0] SERCOM PAD[1] N/A N/A
0x1 SERCOM PAD[2] SERCOM PAD[3] N/A N/A
0x2 SERCOM PAD[0] N/A SERCOM PAD[2] SERCOM PAD[3]
0x3 Reserved
Bits 15:13 – SAMPR[2:0] Sample Rate
These bits select the sample rate.
These bits are not synchronized.
SAMPR[2:0] Description
0x0 16x over-sampling using arithmetic baud rate generation.
0x1 16x over-sampling using fractional baud rate generation.
0x2 8x over-sampling using arithmetic baud rate generation.
0x3 8x over-sampling using fractional baud rate generation.
0x4 3x over-sampling using arithmetic baud rate generation.
0x5-0x7 Reserved
Bit 8 – IBON Immediate Buffer Overflow Notification
This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer
overflow occurs.
Value Description
0
STATUS.BUFOVF is asserted when it occurs in the data stream.
1
STATUS.BUFOVF is asserted immediately upon buffer overflow.
Bit 7 – RUNSTDBY Run In Standby
This bit defines the functionality in standby sleep mode.
This bit is not synchronized.
RUNSTDBY External Clock Internal Clock
0x0 External clock is disconnected
when ongoing transfer is
finished. All reception is
dropped.
Generic clock is disabled when ongoing transfer is
finished. The device will not wake up on either Receive
Start or Transfer Complete interrupt unless the
appropriate ONDEMAND bits are set in the clocking
chain.
0x1 Wake on Receive Start or
Receive Complete interrupt.
Generic clock is enabled in all sleep modes. Any
interrupt can wake up the device.
SAM D21 Family
SERCOM USART
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 489