Datasheet

Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear

enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and

disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).

An interrupt request is generated when the interrupt flag is set and if the corresponding interrupt is

enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is

disabled, or the USART is reset. For details on clearing interrupt flags, refer to the INTFLAG register

description.

The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally

enabled for interrupt requests. Refer to Nested Vector Interrupt Controller for details.

Related Links

11.2 Nested Vector Interrupt Controller

26.6.4.3 Events

Not applicable.

26.6.5 Sleep Mode Operation

The behavior in sleep mode is depending on the clock source and the Run In Standby bit in the Control A

• Internal clocking, CTRLA.RUNSTDBY=1: GCLK_SERCOMx_CORE can be enabled in all sleep

modes. Any interrupt can wake up the device.

• External clocking, CTRLA.RUNSTDBY=1: The Receive Start and the Receive Complete interrupt(s)

can wake up the device.

• Internal clocking, CTRLA.RUNSTDBY=0: Internal clock will be disabled, after any ongoing transfer

was completed. The Receive Start and the Receive Complete interrupt(s) can wake up the device.

• External clocking, CTRLA.RUNSTDBY=0: External clock will be disconnected, after any ongoing

transfer was completed. All reception will be dropped.

26.6.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers

need to be synchronized when written or read.

The following bits are synchronized when written:

• Software Reset bit in the CTRLA register (CTRLA.SWRST)

• Enable bit in the CTRLA register (CTRLA.ENABLE)

• Receiver Enable bit in the CTRLB register (CTRLB.RXEN)

• Transmitter Enable bit in the Control B register (CTRLB.TXEN)

Note: CTRLB.RXEN is write-synchronized somewhat differently. See also 26.8.2 CTRLB for details.

Required write-synchronization is denoted by the "Write-Synchronized" property in the register

description.