Datasheet

Table 26-5. Module Request for SERCOM USART
Condition Request
DMA Interrupt Event
Standard (DRE): Data Register Empty
FIFO (DRE): at least TXTRHOLD locations in TX FIFO are
empty
Yes
(request cleared when
data is written)
Yes NA
Standard (RXC): Receive Complete
FIFO (RXC): at least RXTRHOLD data available in RX
FIFO, or a last word available and length frame reception
completed.
Yes
(request cleared when
data is read)
Yes
Standard (TXC): Transmit Complete
FIFO (TXC): Transmit Complete and TX FIFO is empty
NA Yes
Receive Start (RXS) NA Yes
Clear to Send Input Change (CTSIC) NA Yes
Receive Break (RXBRK) NA Yes
Error (ERROR) NA Yes
26.6.4.1 DMA Operation
The USART generates the following DMA requests:
• Data received (RX): The request is set when data is available in the receive FIFO. The request is
cleared when DATA is read.
• Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is
cleared when DATA is written.
• Data received (RX): The request is set when data is available in the receive FIFO or if at least
RXTRHOLD data are available in the RX FIFO when FIFO operation is enabled. The request is
cleared when DATA is read.
• Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty or if at least
TXTRHOLD data locations are empty in the TX FIFO, when FIFO operation is enabled. The
request is cleared when DATA is written.
26.6.4.2 Interrupts
The USART has the following interrupt sources. These are asynchronous interrupts, and can wake up the
device from any sleep mode:
• Data Register Empty (DRE)
• Receive Complete (RXC)
• Transmit Complete (TXC)
• Receive Start (RXS)
• Clear to Send Input Change (CTSIC)
• Received Break (RXBRK)
• Error (ERROR)
SAM D21 Family
SERCOM USART
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Datasheet Complete
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