Datasheet

Depending the TX FIFO Threshold settings (CTRLC.TXTRHOLD), Interrupt Flag Status and Clear
register (INTFLAG.DRE) indicates that the register is empty and ready for new data. DATA to TX FIFO
should only be written to when INTFLAG.DRE is set.
If the USART is halted when debugging, the CPUWRPTR pointer can be accessed by writting the
CPUWRPTR bits in FIFOPTR register (FIFOPTR.CPUWRPTR). These bits will not increment if a new
data is written into the TX FIFO memory.
26.6.3.9.2 Pointer Operation when DATA Reception
As in normal operation, when the first stop bit is received and a complete serial frame is present in the
receive shift register, the contents of the shift register will be moved into the RX FIFO, and the
USARTWRPTR is incremented by one. Depending the RX FIFO Threshold settings
(CTRLC.RXTRHOLD), the Receive Complete interrupt flag (INTFLAG.RXC) is set, and the DATA can be
read from RX FIFO. When a DATA is read, the CPURDPTR is incremented. As long as data are present
in RX FIFO (FIFOSPACE.RXSPACE != 0), the CPU can read these data by accessing the DATA register.
All pointers increment to their maximum value, dictated by CTRLC.DATA32B bit, and then rolls over to ‘0’.
When both RX shifter and RX FIFO are full, the Buffer Overflow status bit is set (STATUS.BUFOVF) and
optional ERROR interrupt is generated. The data will not be stored while BUFOVF is ‘1’, effectively
disabling the module until software reads RX FIFO.
If the USART is halted when debugging, the RX FIFO CPU read pointer can be accessed by writting the
CPURDPTR bits in FIFOPTR register (FIFOPTR.CPURDPTR). These bits will not increment if a new
data is read from the RX FIFO memory.
26.6.4 DMA, Interrupts and Events
Table 26-4. Module Request for SERCOM USART
Condition Request
DMA Interrupt Event
Data Register Empty (DRE) Yes
(request cleared when data is written)
Yes NA
Receive Complete (RXC) Yes
(request cleared when data is read)
Yes
Transmit Complete (TXC) NA Yes
Receive Start (RXS) NA Yes
Clear to Send Input Change (CTSIC) NA Yes
Receive Break (RXBRK) NA Yes
Error (ERROR) NA Yes
SAM D21 Family
SERCOM USART
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 482