Datasheet

pointer (USARTRDPTR). All of these pointers reset to ‘0’. The CPUWRPTR and CPURDPTR pointers are
native to the CPU clock domain, while the USARTWRPTR and USARTRDPTR are native to the USART
domain. The location pointed to by the CPUWRPTR is the current TX FIFO. The location pointed to by
the CPURDPTR becomes the current RX FIFO. Writes to DATA register by the CPU will point to TX FIFO.
Reads to DATA register by the CPU will point to RX FIFO. The location pointed to by the
USARTWRPTR / USARTRDPTR is logically the current RX/TX shift registers.
Figure 26-14. FIFO Overview
RX FIFOTX FIFO
DATA DATA
TX Shift RegisterTxD
CPUWRPTR
CPURDPTR
USARTWRPTR
USARTRDPTR
TX FIFO
THRESHOLD
Interrupt /
DMA Req.
Interrupt /
DMA Req.
RX FIFO
THRESHOLD
RX Shift Register TxD
The interrupts and DMA triggers are generated according to FIFO threshold settings in Control C register
(CTRLC.TXTRHOLD, CTRLC.RXTRHOLD).
The Data Register Empty interrupt flag, and the DMA TX trigger respectivly, are generated when the
available place in the TX FIFO is equal or higher than the threshold value defined by the
CTRLC.TXTRHOLD settings. The Transfer complete interrupt is generated when the TX FIFO is empty
and the entire data (including the stop bits) has been transmitted.
The Receive Complete interrupt flag, and the DMA RX trigger respectivly, are generated when the
number of bytes present in the RX FIFO equals or is higher than the threshold value defined by the
CTRLC.RXTRHOLD settings. The ERROR interrupt flag is generated when both RX shifter and the RX
FIFO are full.
The FIFO is fully accessible if the SERCOM is halted, by writting the corresponding CPU FIFO pointer in
the FIFOPTR register. The RX or TX FIFO can be individually cleared, by setting the respective FIFO
Clear bit in the Control B register (CTRLB.FIFOCLR). The FIFO Clear must be written before data
transfer begins. Writing the FIFO Clear bits while a frame is in progress will produce unpredicatable
results.
26.6.3.9.1 Pointer Operation when DATA Transmission
As in normal operation, data transmission is initiated by writing the data to be sent into the TX FIFO, by
accessing the DATA register. CPUWRPTR is incremented by 1 every time the CPU writes a word to the
memory array. Then, the data in TX FIFO will be moved to the shift register when the shift register is
empty and ready to send a new frame, and the USARTRDPTR is incremented by 1. After the shift
register is loaded with data, the data frame will be transmitted.
As long as data are present in TX FIFO (FIFOSPACE.TXSPACE != 0), a new data will be automatically
loaded in the TX shift register when the previous data transmission is completed. All pointers increment to
their maximum value, dictated by CTRLC.DATA32B bit, and then rolls over to ‘0’.
SAM D21 Family
SERCOM USART
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 481