Datasheet

11.2.2 Interrupt Line Mapping
Each of the 29 interrupt lines is connected to one peripheral instance, as shown in the table below. Each
peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear
(INTFLAG) register. The Interrupt flag is set when the Interrupt condition occurs. Each interrupt in the
peripheral can be individually enabled by writing a one to the corresponding bit in the peripheral’s
Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the corresponding bit in the
peripheral’s Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated from the
peripheral when the Interrupt flag is set and the corresponding interrupt is enabled. The interrupt requests
for one peripheral are ORed together on system level, generating one interrupt request for each
peripheral. An interrupt request will set the corresponding Interrupt Pending bit in the NVIC Interrupt
Pending registers (SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it
must be enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC
Interrupt Priority registers IPR0-IPR7 provide a priority field for each interrupt.
Table 11-3. Interrupt Line Mapping
Peripheral Source NVIC Line
EIC NMI – External Interrupt Controller NMI
PM – Power Manager 0
SYSCTRL – System Control 1
WDT – Watchdog Timer 2
RTC – Real-Time Counter 3
EIC – External Interrupt Controller 4
NVMCTRL – Nonvolatile Memory Controller 5
DMAC - Direct Memory Access Controller 6
USB - Universal Serial Bus 7
EVSYS – Event System 8
SERCOM0 – Serial Communication Interface 0 9
SERCOM1 – Serial Communication Interface 1 10
SERCOM2 – Serial Communication Interface 2 11
SERCOM3 – Serial Communication Interface 3 12
SERCOM4 – Serial Communication Interface 4 13
SERCOM5 – Serial Communication Interface 5 14
TCC0 – Timer Counter for Control 0 15
TCC1 – Timer Counter for Control 1 16
TCC2 – Timer Counter for Control 2 17
TC3 – Timer Counter 3 18
TC4 – Timer Counter 4 19
TC5 – Timer Counter 5 20
SAM D21 Family
Processor And Architecture
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 48