Datasheet

data loss may result during debugging. This peripheral can be forced to halt operation during debugging -
refer to the Debug Control (DBGCTRL) register for details.
Related Links
26.8.11 DBGCTRL
26.5.8 Register Access Protection
Registers with write-access can be write-protected optionally by the peripheral access controller (PAC).
PAC Write-Protection is not available for the following registers:
• Interrupt Flag Clear and Status register (INTFLAG)
• Status register (STATUS)
• Data register (DATA)
Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual
register description.
Write-protection does not apply to accesses through an external debugger.
Related Links
11.6 PAC - Peripheral Access Controller
26.5.9 Analog Connections
Not applicable.
26.6 Functional Description
26.6.1 Principle of Operation
The USART uses the following lines for data transfer:
• RxD for receiving
• TxD for transmitting
• XCK for the transmission clock in synchronous operation
USART data transfer is frame based. A serial frame consists of:
• 1 start bit
• From 5 to 9 data bits (MSB or LSB first)
• No, even or odd parity bit
• 1 or 2 stop bits
A frame starts with the start bit followed by one character of data bits. If enabled, the parity bit is inserted
after the data bits and before the first stop bit. After the stop bit(s) of a frame, either the next frame can
follow immediately, or the communication line can return to the idle (high) state. The figure below
illustrates the possible frame formats. Brackets denote optional bits.
Figure 26-2. Frame Formats
Frame
(IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] [St/IDL]
SAM D21 Family
SERCOM USART
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 471