Datasheet

The combined configuration of PORT and the Transmit Data Pinout and Receive Data Pinout bit fields in
the Control A register (CTRLA.TXPO and CTRLA.RXPO, respectively) will define the physical position of
the USART signals in Table 26-2.
Related Links
23. PORT - I/O Pin Controller
26.5.2 Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. The
interrupts can wake up the device from sleep modes.
Related Links
16. PM – Power Manager
26.5.3 Clocks
The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Power Manager.
Refer to Peripheral Clock Masking for details and default status of this clock.
A generic clock (GCLK_SERCOMx_CORE) is required to clock the SERCOMx_CORE. This clock must
be configured and enabled in the Generic Clock Controller before using the SERCOMx_CORE. Refer to
GCLK - Generic Clock Controller for details.
This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Therefore, writing to certain
registers will require synchronization to the clock domains. Refer to Synchronization for further details.
Related Links
26.6.6 Synchronization
15. GCLK - Generic Clock Controller
16.6.2.6 Peripheral Clock Masking
26.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with
this peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for
details.
Related Links
20. DMAC – Direct Memory Access Controller
26.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this
peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt
Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
26.5.6 Events
Not applicable.
26.5.7 Debug Operation
When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is
configured to require periodical service by the CPU through interrupts or similar, improper operation or
SAM D21 Family
SERCOM USART
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 470