Datasheet

– The System Timer is a 24-bit timer clocked by CLK_CPU that extends the functionality of both

the processor and the NVIC. Refer to the Cortex-M0+ Technical Reference Manual for details

(www.arm.com).

• Nested Vectored Interrupt Controller (NVIC)

– External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts.

Software can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor core

are closely coupled, providing low latency interrupt processing and efficient processing of late

arriving interrupts. Refer to 11.2 Nested Vector Interrupt Controller and the Cortex-M0+

Technical Reference Manual for details (www.arm.com).

• System Control Block (SCB)

– The System Control Block provides system implementation information, and system control.

This includes configuration, control, and reporting of the system exceptions. Refer to the

Cortex-M0+ Devices Generic User Guide for details (www.arm.com).

• Micro Trace Buffer (MTB)

– The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the Cortex-

M0+ processor. Refer to section 11.3 Micro Trace Buffer and the CoreSight MTB-M0+

Technical Reference Manual for details (www.arm.com).

11.1.3 Cortex-M0+ Address Map

Table 11-2. Cortex-M0+ Address Map

Address Peripheral

0xE000E000 System Control Space (SCS)

0xE000E010 System Timer (SysTick)

0xE000E100 Nested Vectored Interrupt Controller (NVIC)

0xE000ED00 System Control Block (SCB)

0x41006000 (see also Product Mapping) Micro Trace Buffer (MTB)

11.1.4 I/O Interface

11.1.4.1 Overview

Because accesses to the AMBA

AHB-Lite

™

and the single cycle I/O interface can be made concurrently,

the Cortex-M0+ processor can fetch the next instructions while accessing the I/Os. This enables single

cycle I/O accesses to be sustained for as long as needed. Refer to CPU Local Bus for more information.