Datasheet

25.6.3.1.3 Address Range
The range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK will cause a match.
ADDR.ADDR and ADDR.ADDRMASK can be set to any two addresses, with ADDR.ADDR acting as the
upper limit and ADDR.ADDRMASK acting as the lower limit.
Figure 25-6. Address Range
ADDRMASK rx shift register ADDR
==
Match
25.6.4 DMA Operation
The available DMA interrupts and their depend on the operation mode of the SERCOM peripheral. Refer
to the Functional Description sections of the respective SERCOM mode.
Related Links
26. SERCOM USART
27. SERCOM SPI – SERCOM Serial Peripheral Interface
28. SERCOM I2C – Inter-Integrated Circuit
25.6.5 Interrupts
Interrupt sources are mode-specific. See the respective SERCOM mode chapters for details.
Each interrupt source has its own interrupt flag.
The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt
condition is met.
Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable
Set register (INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear
register (INTENCLR).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or
the SERCOM is reset. For details on clearing interrupt flags, refer to the INTFLAG register description.
The value of INTFLAG indicates which interrupt condition occurred. The user must read the INTFLAG
register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests.
Related Links
11.2 Nested Vector Interrupt Controller
25.6.6 Events
Not applicable.
25.6.7 Sleep Mode Operation
The peripheral can operate in any sleep mode where the selected serial clock is running. This clock can
be external or generated by the internal baud-rate generator.
The SERCOM interrupts can be used to wake up the device from sleep modes. Refer to the different
SERCOM mode chapters for details.
25.6.8 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
SAM D21 Family
SERCOM – Serial Communication Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 466