Datasheet

• Data register (DATA)
• Address register (ADDR)
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-
Protection" property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
Related Links
11.6 PAC - Peripheral Access Controller
25.5.9 Analog Connections
Not applicable.
25.6 Functional Description
25.6.1 Principle of Operation
The basic structure of the SERCOM serial engine is shown in Figure 25-2. Labels in capital letters are
synchronous to the system clock and accessible by the CPU; labels in lowercase letters can be
configured to run on the GCLK_SERCOMx_CORE clock or an external clock.
Figure 25-2. SERCOM Serial Engine
Transmitter
Baud Rate Generator
Equal
Selectable
Internal Clk
(GCLK)
Ext Clk
Receiver
Address Match
Baud Rate Generator
TX Shift Register
RX Shift Register
RX BufferStatus
BAUD TX DATA ADDR/ADDRMASK
RX DATASTATUS
1/- /2- /16
The transmitter consists of a single write buffer and a shift register.
The receiver consists of a one-level (I
2
C), two-level (USART, SPI) receive buffer and a shift register.
The baud-rate generator is capable of running on the GCLK_SERCOMx_CORE clock or an external
clock.
Address matching logic is included for SPI and I
2
C operation.
SAM D21 Family
SERCOM – Serial Communication Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 462