Datasheet

25.3 Block Diagram
Figure 25-1. SERCOM Block Diagram
TX/RX DATA
CONTROL/STATUS
Mode n
SERCOM
BAUD/ADDR
Transmitter
Register Interface
Serial Engine
Receiver
Mode 0
Mode 1
Baud Rate
Generator
Address
Match
Mode Specific
PAD[3:0]
25.4 Signal Description
See the respective SERCOM mode chapters for details.
Related Links
26. SERCOM USART
27. SERCOM SPI – SERCOM Serial Peripheral Interface
28. SERCOM I2C – Inter-Integrated Circuit
25.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
25.5.1 I/O Lines
Using the SERCOM I/O lines requires the I/O pins to be configured using port configuration (PORT).
The SERCOM has four internal pads, PAD[3:0], and the signals from I2C, SPI and USART are routed
through these SERCOM pads via a multiplexer. The configuration of the multiplexer is available from the
different SERCOM modes. Refer to the mode specific chapters for details.
Related Links
26. SERCOM USART
27. SERCOM SPI – SERCOM Serial Peripheral Interface
28. SERCOM I2C – Inter-Integrated Circuit
23. PORT - I/O Pin Controller
26.3 Block Diagram
25.5.2 Power Management
The SERCOM can operate in any Sleep mode provided the selected clock source is running. SERCOM
interrupts can be configured to wake the device from Sleep modes.
SAM D21 Family
SERCOM – Serial Communication Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 460