Datasheet

11. Processor And Architecture
11.1 Cortex M0+ Processor
The SAM D21 implements the ARM
®
Cortex
®
-M0+ processor, based on the ARMv6 Architecture and
Thumb
®
-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0
core, and upward compatible to Cortex-M3 and M4 cores. The ARM Cortex-M0+ implemented is revision
r0p1. For more information refer to http://www.arm.com.
11.1.1 Cortex M0+ Configuration
Table 11-1. Cortex M0+ Configuration
Features Configurable option Device configuration
Interrupts External interrupts 0-32 28
Data endianness Little-endian or big-endian Little-endian
SysTick timer Present or absent Present
Number of watchpoint comparators 0, 1, 2 2
Number of breakpoint comparators 0, 1, 2, 3, 4 4
Halting debug support Present or absent Present
Multiplier Fast or small Fast (single cycle)
Single-cycle I/O port Present or absent Present
Wake-up interrupt controller Supported or not supported Not supported
Vector Table Offset Register Present or absent Present
Unprivileged/Privileged support Present or absent Absent
(1)
Memory Protection Unit Not present or 8-region Not present
Reset all registers Present or absent Absent
Instruction fetch width 16-bit only or mostly 32-bit 32-bit
Note: 
1. All software run in Privileged mode only.
The ARM Cortex-M0+ core has the following two bus interfaces:
Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all
system memory, which includes Flash and RAM.
Single 32-bit I/O port bus interfacing to the PORT with 1-cycle loads and stores.
11.1.2 Cortex-M0+ Peripherals
System Control Space (SCS)
The processor provides debug through registers in the SCS. Refer to the Cortex-M0+
Technical Reference Manual for details (www.arm.com).
System Timer (SysTick)
SAM D21 Family
Processor And Architecture
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 46