Datasheet

24.8.5 Interrupt Enable Clear
Name: INTENCLR
Offset: 0x10
Reset: 0x00000000
Property: Write-Protected
Bit 31 30 29 28 27 26 25 24
EVDn EVDn EVDn EVDn
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
OVRn OVRn OVRn OVRn
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
EVDn EVDn EVDn EVDn EVDn EVDn EVDn EVDn
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OVRn OVRn OVRn OVRn OVRn OVRn OVRn OVRn
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 27,26,25,24,15,14,13,12,11,10,9,8 – EVDn Channel n Event Detection Interrupt Enable [n=11..0]
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Event Detected Channel n Interrupt Enable bit, which disables the
Event Detected Channel n interrupt.
Value Description
0
The Event Detected Channel n interrupt is disabled.
1
The Event Detected Channel n interrupt is enabled.
Bits 19,18,17,16,7,6,5,4,3,2,1,0 – OVRn Channel n Overrun Interrupt Enable [n=11..0]
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Channel n Interrupt Enable bit, which disables the Overrun
Channel n interrupt.
Value Description
0
The Overrun Channel n interrupt is disabled.
1
The Overrun Channel n interrupt is enabled.
SAM D21 Family
EVSYS – Event System
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 456