Datasheet

24.4 Signal Description
Not applicable.
24.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
24.5.1 I/O Lines
Not applicable.
24.5.2 Power Management
The EVSYS can be used to wake up the CPU from all sleep modes, even if the clock used by the EVSYS
channel and the EVSYS bus clock are disabled. Refer to the PM – Power Manager for details on the
different sleep modes.
In all sleep modes, although the clock for the EVSYS is stopped, the device still can wake up the EVSYS
clock. Some event generators can generate an event when their clocks are stopped.
Related Links
16. PM – Power Manager
24.5.3 Clocks
The EVSYS bus clock (CLK_EVSYS_APB) can be enabled and disabled in the Main Clock module, and
the default state of CLK_EVSYS_APB can be found in Peripheral Clock Masking.
Each EVSYS channel has a dedicated generic clock (GCLK_EVSYS_CHANNEL_n). These are used for
event detection and propagation for each channel. These clocks must be configured and enabled in the
generic clock controller before using the EVSYS. Refer to GCLK - Generic Clock Controller for details.
Related Links
16.6.2.6 Peripheral Clock Masking
15. GCLK - Generic Clock Controller
24.5.4 DMA
Not applicable.
24.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the EVSYS interrupts requires
the interrupt controller to be configured first. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
24.5.6 Events
Not applicable.
24.5.7 Debug Operation
When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is
configured to require periodical service by the CPU through interrupts or similar, improper operation or
data loss may result during debugging. This peripheral can be forced to halt operation during debugging.
SAM D21 Family
EVSYS – Event System
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 438