Datasheet

23.8.13 Pin Configuration
Name: PINCFG
Offset: 0x40 + n*0x01 [n=0..31]
Reset: 0x00
Property: PAC Write-Protection
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0
consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT
registers, with a 0x80 address spacing. For example, the register address offset for the Data
Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for
the DIR register for group 1 (PB00 to PB31) is 0x80.
There are up to 32 Pin Configuration registers in each PORT group, one for each I/O line.
Bit 7 6 5 4 3 2 1 0
DRVSTR PULLEN INEN PMUXEN
Access
RW RW RW RW
Reset 0 0 0 0
Bit 6 – DRVSTR Output Driver Strength Selection
This bit controls the output driver strength of an I/O pin configured as an output.
Value Description
0
Pin drive strength is set to normal drive strength.
1
Pin drive strength is set to stronger drive strength.
Bit 2 – PULLEN Pull Enable
This bit enables the internal pull-up or pull-down resistor of an I/O pin configured as an input.
Value Description
0
Internal pull resistor is disabled, and the input is in a high-impedance configuration.
1
Internal pull resistor is enabled, and the input is driven to a defined logic level in the absence
of external input.
Bit 1 – INEN Input Enable
This bit controls the input buffer of an I/O pin configured as either an input or output.
Writing a zero to this bit disables the input buffer completely, preventing read-back of the Physical Pin
state when the pin is configured as either an input or output.
Value Description
0
Input buffer for the I/O pin is disabled, and the input value will not be sampled.
1
Input buffer for the I/O pin is enabled, and the input value will be sampled when required.
SAM D21 Family
PORT - I/O Pin Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 435