Datasheet

23.8.12 Peripheral Multiplexing n
Name: PMUX
Offset: 0x30 + n*0x01 [n=0..15]
Reset: 0x00
Property: PAC Write-Protection
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0
consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT
registers, with a 0x80 address spacing. For example, the register address offset for the Data
Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for
the DIR register for group 1 (PB00 to PB31) is 0x80.
There are up to 16 Peripheral Multiplexing registers in each group, one for every set of two subsequent
I/O lines. The n denotes the number of the set of I/O lines.
Bit 7 6 5 4 3 2 1 0
PMUXO[3:0] PMUXE[3:0]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bits 7:4 – PMUXO[3:0] Peripheral Multiplexing for Odd-Numbered Pin
These bits select the peripheral function for odd-numbered pins (2*n + 1) of a PORT group, if the
corresponding PINCFGy.PMUXEN bit is '1'.
Not all possible values for this selection may be valid. For more details, refer to the I/O Multiplexing and
Considerations.
PMUXO[3:0] Name Description
0x0 A Peripheral function A selected
0x1 B Peripheral function B selected
0x2 C Peripheral function C selected
0x3 D Peripheral function D selected
0x4 E Peripheral function E selected
0x5 F Peripheral function F selected
0x6 G Peripheral function G selected
0x7 H Peripheral function H selected
0x8 I Peripheral function I selected
0x9-0xF - Reserved
SAM D21 Family
PORT - I/O Pin Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 433