Datasheet

23.8.11 Write Configuration
Name: WRCONFIG
Offset: 0x28
Reset: 0x00000000
Property: PAC Write-Protection
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0
consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT
registers, with a 0x80 address spacing. For example, the register address offset for the Data
Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for
the DIR register for group 1 (PB00 to PB31) is 0x80.
This write-only register is used to configure several pins simultaneously with the same configuration
and/or peripheral multiplexing.
In order to avoid side effect of non-atomic access, 8-bit or 16-bit writes to this register will have no effect.
Reading this register always returns zero.
Bit 31 30 29 28 27 26 25 24
HWSEL WRPINCFG WRPMUX PMUX[3:0]
Access
W W W W W W W
Reset 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
PULLEN INEN PMUXEN
Access
W W W
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8
PINMASK[15:8]
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PINMASK[7:0]
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Bit 31 – HWSEL Half-Word Select
This bit selects the half-word field of a 32-PORT group to be reconfigured in the atomic write operation.
This bit will always read as zero.
Value Description
0
The lower 16 pins of the PORT group will be configured.
1
The upper 16 pins of the PORT group will be configured.
SAM D21 Family
PORT - I/O Pin Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 430