Datasheet

23.8.8 Data Output Value Toggle
Name: OUTTGL
Offset: 0x1C
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to toggle the drive level of one or more output I/O pins, without doing a read-
modify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT),
Data Output Value Set (OUTSET) and Data Output Value Clear (OUTCLR) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0
consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT
registers, with a 0x80 address spacing. For example, the register address offset for the Data
Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for
the DIR register for group 1 (PB00 to PB31) is 0x80.
Bit 31 30 29 28 27 26 25 24
OUTTGL[31:24]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
OUTTGL[23:16]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
OUTTGL[15:8]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OUTTGL[7:0]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bits 31:0 – OUTTGL[31:0] PORT Data Output Value Toggle
Writing '0' to a bit has no effect.
Writing '1' to a bit will toggle the corresponding bit in the OUT register, which inverts the output drive level
for I/O pins configured as outputs via the Data Direction register (DIR). For pins configured as inputs via
Data Direction register (DIR) with pull enabled via the Pull Enable register (PULLEN), these bits will
toggle the input pull direction.
Value Description
0
The corresponding I/O pin in the PORT group will keep its configuration.
1
The corresponding OUT bit value is toggled.
SAM D21 Family
PORT - I/O Pin Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 427