Datasheet

23.8.1 Data Direction
Name: DIR
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to configure one or more I/O pins as an input or output. This register can be
manipulated without doing a read-modify-write operation by using the Data Direction Toggle (DIRTGL),
Data Direction Clear (DIRCLR) and Data Direction Set (DIRSET) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0
consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT
registers, with a 0x80 address spacing. For example, the register address offset for the Data
Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for
the DIR register for group 1 (PB00 to PB31) is 0x80.
Bit 31 30 29 28 27 26 25 24
DIR[31:24]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DIR[23:16]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DIR[15:8]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DIR[7:0]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bits 31:0 – DIR[31:0] Port Data Direction
These bits set the data direction for the individual I/O pins in the PORT group.
Value Description
0
The corresponding I/O pin in the PORT group is configured as an input.
1
The corresponding I/O pin in the PORT group is configured as an output.
SAM D21 Family
PORT - I/O Pin Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 417