Datasheet

23.7 Register Summary
The I/O pins are assembled in pin groups with up to 32 pins. Group 0 consists of the PA pins, and group 1
is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For
example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is
0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80.
Offset Name Bit Pos.
0x00 DIR
7:0 DIR[7:0]
15:8 DIR[15:8]
23:16 DIR[23:16]
31:24 DIR[31:24]
0x04 DIRCLR
7:0 DIRCLR[7:0]
15:8 DIRCLR[15:8]
23:16 DIRCLR[23:16]
31:24 DIRCLR[31:24]
0x08 DIRSET
7:0 DIRSET[7:0]
15:8 DIRSET[15:8]
23:16 DIRSET[23:16]
31:24 DIRSET[31:24]
0x0C DIRTGL
7:0 DIRTGL[7:0]
15:8 DIRTGL[15:8]
23:16 DIRTGL[23:16]
31:24 DIRTGL[31:24]
0x10 OUT
7:0 OUT[7:0]
15:8 OUT[15:8]
23:16 OUT[23:16]
31:24 OUT[31:24]
0x14 OUTCLR
7:0 OUTCLR[7:0]
15:8 OUTCLR[15:8]
23:16 OUTCLR[23:16]
31:24 OUTCLR[31:24]
0x18 OUTSET
7:0 OUTSET[7:0]
15:8 OUTSET[15:8]
23:16 OUTSET[23:16]
31:24 OUTSET[31:24]
0x1C OUTTGL
7:0 OUTTGL[7:0]
15:8 OUTTGL[15:8]
23:16 OUTTGL[23:16]
31:24 OUTTGL[31:24]
0x20 IN
7:0 IN[7:0]
15:8 IN[15:8]
23:16 IN[23:16]
31:24 IN[31:24]
SAM D21 Family
PORT - I/O Pin Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 415